It wrapped the gate around the channel on three sides to provide better electrostatic control. To address this, the industry moved to an entirely different transistor architecture called aįinFET. Basically, the distance between the source and drain became so small that current would leak across the channel when it wasn’t supposed to, because the gate electrode struggled to deplete the channel of charge carriers. Applying a large enough voltage to the gate (relative to the source) creates a layer of mobile charge carriers in the channel region that allows current to flow between the source and drain.Īs we scaled down the classic planar transistors, what device physicists call short-channel effects took center stage. In the planar version in use in advanced microprocessors up to 2011, the MOSFET’s gate stack is situated just above the channel region and is designed to project an electric field into the channel region. The channel region has the opposite doping to the source and drain. The source and drain are chemically doped to make them both either rich in mobile electrons (
To understand these trade-offs and how they’re leading us inevitably toward 3D-stacked CMOS, you need a bit of background on transistor operation.Įvery metal-oxide-semiconductor field-effect transistor, or MOSFET, has the same set of basic parts: the gate stack, the channel region, the source, and the drain. We believe this 3D-stacked complementary metal-oxide semiconductor (CMOS), or CFET (complementary field-effect transistor), will be the key to extending Moore’s Law into the next decade.Ĭontinuous innovation is an essential underpinning of Moore’s Law, but each improvement comes with trade-offs. Crucially, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the foundation of all the logic circuits of the last several decades. We’ve created experimental devices that stack atop each other, delivering logic that is 30 to 50 percent smaller.
So where will we turn for future scaling? We will continue to look to the third dimension. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.
Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.Īlong this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption.
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